Find where chip designagents break
Benchmarks generated at scale, correct by construction
Empowering the next generation of Hardware-design AI models, by closing the gap of Verilog data scarcity, inconsistent quality, and restrictive licensing.
veriRCA
Most benchmarks ask whether an agent can make a failing test pass. veriRCA asks whether it understood why the test was failing.
In real chip design, debugging is root-cause analysis. A failing simulation or a timing violation is only a symptom, and a change that silences it can leave the underlying bug in place or push it somewhere else in the design. An agent that chases symptoms can look productive on a test suite while being unsafe in a real flow.
veriRCA evaluates the whole debugging loop. For every task, the agent performs root-cause analysis on a buggy design, explains in plain language what went wrong and where, and only then repairs it. The fix and the explanation are graded separately and both must be right, so a patch that happens to work without a correct diagnosis earns no credit.
How a task works
Observe
The agent receives a design that contains a bug, along with the symptom the bug produces.
Diagnose
It performs root-cause analysis and writes down what went wrong, where, and why.
Fix
Only after the diagnosis does it propose a repair to the design.
Grade
The repair is checked for correctness, and the explanation is checked against the true cause of the bug.
Rewards understanding, not workarounds
Because the explanation is graded, shortcuts such as special-casing the failing behavior or masking the symptom do not pass. An agent has to show it found the actual defect.
Broad coverage
Tasks span 18 design families and 13 bug categories, with an average of three tasks per design. Scores reflect how an agent debugs across many kinds of hardware and failure modes, not how it handles one lucky design.
Want to see how your chip design agent performs on veriRCA?
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The ARTL agentic AI platform models chip architectures in Python and seamlessly converts them into Verilog using our proprietary Python-to-Verilog compiler. This pipeline generates novel, fully verified, and copyright-free Verilog datasets at scale to train the next generation of AI models.
Microarchitecture Exploration
Evaluate Power, Performance, and Area (PPA) tradeoffs directly on the Python model prior to generating RTL.
Automated Verification
Automatically generate testbenches for each design to ensure rigorous verification against the original Python model.
Architectural Diversity
Generate multiple architectural variations for every design—each independently tested, synthesized, and analyzed.
Human-Like Code Styling
Leverage diverse syntax generation to produce rich, varied coding styles, avoiding predictable machine-generated patterns.
Targeted Bug Injection
Train models for root-cause analysis using sophisticated bug injection techniques targeting all stages of the design cycle.
Timing Closure Training
Utilize auto-pipelining technology to create designs with varying pipeline depths, simulating realistic timing violations.
Golden & Buggy Datasets
Deliver fully annotated datasets encompassing both correct-by-construction designs and explicitly flawed variations.
Dynamic Generation
Generate new designs, complex edge cases, and specific logic bugs entirely on demand.
Seamless Integration
Integrate seamlessly with industry-standard EDA workflows and open-source hardware design flows.
Proven in Complex Domains
Showcased across a multitude of complex designs, including ML accelerators, modems, SmartNICs, and cryptography.
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Reach out today to see how ARTL can power your hardware-design AI models.